Exploring CPU Clock change on MVEBU

Re: Exploring CPU Clock change on MVEBU

CyberPK — Wed, 13 Mar 2024 10:34:01 -0500

In my WD MyCloud Mirror Gen2 I've found an area near the cpu that appear to contain some jumpers ready to setup pull-up or pull-down resistors in the area of the MPP pins.
So I've modified the uboot to read the Sar value

sed -i '640 i mvOsPrintf("satrVal: 0x%x\\n", satrVal);' board/mv_ebu/a38x/armada_38x_family/ctrlEnv/mvCtrlEnvLib.c

and after some tries I've mapped them as follow:

j1  -> bit 13
j2
j3  -> bit  8
j4
j5  -> bit 2
j6
j7
j8
j9  -> bit 3
j10 -> bit 1
j11 -> bit 6
j12 -> bit 5
j13 -> bit 4
j14 -> bit 12
j15 -> bit 15
j16 -> bit 21
j17

I was not able to map the empty ones.

The relevant bit of the Sar to configure the clock are the bit 10-14. So to change the cpu clock are useful j1 and j14.
Inverting the setting of j14 on the board, the Sar switch from 0x8 to 0xC on the CPU Subsystem Clock Frequency Options bit field.
Using the 2 of the 5 bits of the CPU Subsystem Clock Frequency Options field that I've found, I can set it to 0x0, 0x8 and 0xC that translates in 666Mhz, 1333Mhz and 1600Mhz.

So, finally I've managed to clock the cpu@1600Mhz. Now I'll test it to check if it's stable.

Re: Exploring CPU Clock change on MVEBU

CyberPK — Tue, 12 Mar 2024 12:19:21 -0500

I've found and read the "88F6810, 88F6820, and 88F6828 ARMADA® 380, 385, and 388 High-Performance Single/Dual CPU System on Chip Hardware Specifications", and I think you're true about the hardware configuration.
Compared the uboot from devices with the same cpu but different clock, and couldn't find any indication that it's setup via software.
Probably, the only way to set the clock is pulling up and down some mpp.

***EDIT***
I've read the marking on the cpu of my device, and I've found the speed code is C133 = Commercial 1333Mhz, so anyway I think it isn't graded for higher clock.

Re: Exploring CPU Clock change on MVEBU

CyberPK — Mon, 11 Mar 2024 12:13:12 -0500

It could be useful to gather any data from the i2c bus (it's an eeprom?). Also any hires image of the board to search for an eeprom. I'll dismount mine in the next days.
If anyone can activate in the dts the i2c bus and gather any useful data maybe helpful in understanding if the cpu speed and memory could me modified by software.

Re: Exploring CPU Clock change on MVEBU

sudos — Wed, 06 Mar 2024 22:19:15 -0600

I'm slightly interested in this as the Kace M300 has DDR3-1333 chips on the board (4x Micron D9LLF chips) and the clock speed on the RAM side is by default set to 1066. if there's any similarities between the Armada 310 and 370 in that way it might be possible to also increase the RAM speed on the 310's memory bus for a small bump in performance. It's my understanding these were put in for a better price per chip.

Re: Exploring CPU Clock change on MVEBU

CyberPK — Wed, 06 Mar 2024 17:07:49 -0600

Poking around I found a valid i2c device (i2c0) that I've managed to read, but cannot understand if contains any useful data. It appear to have 2 valid addresses: 0x13 and 0x64, and only 0x13 returns 256 byte of data that I cannot translate into anything useful.
Any feedback?

*** EDIT ***
Removed the read memory, because was not useful to the topic.

Re: Exploring CPU Clock change on MVEBU

bodhi — Wed, 06 Mar 2024 00:02:21 -0600

1000001101000 Wrote:
-------------------------------------------------------
> I spent some time looking at the clock speed of
> some armada-370 devices a while back. It appeared
> in the datasheet that the relevant values had to
> be set right when the CPU came up either by pull
> up/down resistors on certain pins or via the
> bootrom. I got the impression this all happened
> before uboot even started.

Yes. The SatR registers (i.e.strapping) set this, IIRC. Boot device (SPI or NAND) are also from there. We probably need HW mods to make overclock possible.

Re: Exploring CPU Clock change on MVEBU

1000001101000 — Tue, 05 Mar 2024 23:23:31 -0600

I spent some time looking at the clock speed of some armada-370 devices a while back. It appeared in the datasheet that the relevant values had to be set right when the CPU came up either by pull up/down resistors on certain pins or via the bootrom. I got the impression this all happened before uboot even started.

Re: Exploring CPU Clock change on MVEBU

CyberPK — Mon, 04 Mar 2024 17:52:19 -0600

I haven't still found the solution to change the clock in uboot. Anyone known a board clocked at 1600mhz instead of the 1333 of the WD MyCloud Mirror Gen2? I've already verified that my board has ddr3 1600 (800Mhz), so I should be safe.
In the meantime I've adapted a patch from openwrt to enable cpu frequency scaling on kernel 6.7.7

Source: https://forum.openwrt.org/t/cpu-frequency-scaling-driver-for-mvebu-wrt3200acm-etc/2808/
original patch: lore.kernel.org/linux-pm/1435903917-20486-1-git-send-email-gregory.clement@free-electrons.com/

Exploring CPU Clock change on MVEBU

CyberPK — Fri, 01 Mar 2024 19:10:31 -0600

I'm trying to change the CPU clock on a MVEBU based WD MyCloud Mirror Gen2.

I've studied the u-boot sources from WD (https://support-en.wd.com/app/products/product-detailweb/p/137 WDMyCloud_Mirror_GPL_v2.31.204_20191206.tar.gz), a customized version of uboot 2013.01-14t3 (github mirror https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/tree/u-boot-2013.01-14t3)

On my device I've a modified uboot re-enabling save env (https://forum.doozan.com/read.php?2,35291) and now I'm trying to understand how-to change the cpu speed.

If I'm not wrong, that configuration could be saved in SatR, and could be loaded from TWSI (i2C device?). In the uboot terminal I've tried only the SatR list and SatR read command, unsuccessfully.

Looking at mvCtrlEnvLib.c, mvCtrlEnvRegs.h, mvCpu.c, cmd_sar38x.c and mvOs.h, I've undestood that the CPU configuration is read through the call (mvCpu.c)mvCpuPclkGet -> (mvCtrlEnvLib.c)mvCtrlCpuDdrL2FreqGet -> (mvOs.h)MV_REG_READ -> (mvOs.h)MV_MEMIO_LE32_READ(INTER_REGS_BASE | (offset)) -> (mvOs.h)MV_MEMIO32_READ -> ((*((volatile unsigned int*)(addr))))

The frequencies are defined in mvCtrlEnvRegs.h->MV_SAR_FREQ_MODES

Any help to go any further? Where is really stored the value, and how can ba changed? The TWSI must be reenabled?

*** edit ***
at https://forum.doozan.com/read.php?2,35291,136911#msg-136911 I've posted a first unsuccessful attemp. Still searching for help.