armada 370 L2 cache November 11, 2020 05:33PM |
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Re: armada 370 L2 cache November 11, 2020 06:37PM |
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Re: armada 370 L2 cache November 12, 2020 05:16AM |
Admin Registered: 14 years ago Posts: 19,306 |
[ 0.608363] mvebu-pmsu: CPU idle is currently broken on Armada 38x: disabling
Re: armada 370 L2 cache November 12, 2020 08:29AM |
Registered: 6 years ago Posts: 258 |
Re: armada 370 L2 cache November 12, 2020 09:01AM |
Registered: 6 years ago Posts: 258 |
[ 0.000000] Aurora cache controller enabled, 4 ways, 256 kB [ 0.000000] Aurora: CACHE_ID 0x00000100, AUX_CTRL 0x1a086302
root@ls421de-Buster:~# busybox devmem 0xd0008100 0x00000001 root@ls421de-Buster:~# busybox devmem 0xd0008104 0x1A086302
Re: armada 370 L2 cache November 12, 2020 02:11PM |
Admin Registered: 14 years ago Posts: 19,306 |
[ 0.000000] L2C: DT/platform modifies aux control register: 0x12086300 -> 0x1a086302 [ 0.000000] Aurora cache controller enabled, 4 ways, 256 kB [ 0.000000] Aurora: CACHE_ID 0x00000100, AUX_CTRL 0x1a086302
Re: armada 370 L2 cache November 12, 2020 02:58PM |
Registered: 6 years ago Posts: 258 |
Re: armada 370 L2 cache November 12, 2020 02:59PM |
Admin Registered: 14 years ago Posts: 19,306 |
root@Mirabox:~# busybox devmem 0xd0008100 0x00000000 root@Mirabox:~# busybox devmem 0xd0008104 0x12086300
Re: armada 370 L2 cache November 12, 2020 03:14PM |
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Re: armada 370 L2 cache November 12, 2020 03:23PM |
Admin Registered: 14 years ago Posts: 19,306 |
Re: armada 370 L2 cache November 12, 2020 04:47PM |
Admin Registered: 14 years ago Posts: 19,306 |
root@Mirabox:~# busybox devmem 0xd0008100 0x00000000 root@Mirabox:~# busybox devmem 0xd0008104 0x12086300
Re: armada 370 L2 cache November 13, 2020 10:40AM |
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Re: armada 370 L2 cache November 13, 2020 12:13PM |
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Re: armada 370 L2 cache November 13, 2020 04:38PM |
Admin Registered: 14 years ago Posts: 19,306 |
[ 0.000000] L2C: DT/platform modifies aux control register: 0x12086300 -> 0x1a086302 [ 0.000000] Aurora cache controller enabled, 4 ways, 256 kB [ 0.000000] Aurora: CACHE_ID 0x00000100, AUX_CTRL 0x1a086302
Re: armada 370 L2 cache November 13, 2020 06:39PM |
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Re: armada 370 L2 cache November 13, 2020 07:33PM |
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Re: armada 370 L2 cache November 13, 2020 09:19PM |
Admin Registered: 14 years ago Posts: 19,306 |
Re: armada 370 L2 cache November 13, 2020 11:52PM |
Admin Registered: 14 years ago Posts: 19,306 |
[ 0.000000] L2C: DT/platform modifies aux control register: 0x12086300 -> 0x1a086302 [ 0.000000] Aurora cache controller enabled, 4 ways, 256 kB [ 0.000000] Aurora: CACHE_ID 0x00000100, AUX_CTRL 0x1a086302
root@Mirabox:/localdisk# dmesg | grep -i 'cpu idle' [ 0.559609] mvebu-pmsu: CPU idle is currently broken: disabling
root@Mirabox:/localdisk# busybox devmem 0xd0008100 0x00000001 root@Mirabox:/localdisk# busybox devmem 0xd0008104 0x1A086302
-rw-r--r-- 1 root root 489M Mar 26 2017 bigfile_dockstar
root@Mirabox:/localdisk# time cp -av /mnt/nfs/tldplug/localdisk/bigfile_dockstar . '/mnt/nfs/tldplug/localdisk/bigfile_dockstar' -> './bigfile_dockstar' real 0m47.378s user 0m0.029s sys 0m23.374s
root@Mirabox:/localdisk# time cp -a /mnt/nfs/tldplug/localdisk/bigfile_dockstar . real 0m25.415s user 0m0.019s sys 0m10.592s
Re: armada 370 L2 cache November 14, 2020 07:14AM |
Registered: 6 years ago Posts: 183 |
Re: armada 370 L2 cache November 14, 2020 07:15AM |
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Re: armada 370 L2 cache November 14, 2020 07:16AM |
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Re: armada 370 L2 cache November 14, 2020 07:36AM |
Admin Registered: 14 years ago Posts: 19,306 |
Quote
The Hardware coherency cannot be enabled in kernel upstream
Re: armada 370 L2 cache November 14, 2020 12:06PM |
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Re: armada 370 L2 cache November 14, 2020 02:44PM |
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Re: armada 370 L2 cache November 14, 2020 04:01PM |
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Re: armada 370 L2 cache November 14, 2020 04:17PM |
Admin Registered: 14 years ago Posts: 19,306 |
- if (is_smp()) { - if (cachepolicy != CPOLICY_WRITEALLOC) { - pr_warn("Forcing write-allocate cache policy for SMP\n"); - cachepolicy = CPOLICY_WRITEALLOC; - } - if (!(initial_pmd_value & PMD_SECT_S)) { - pr_warn("Forcing shared mappings for SMP\n"); - initial_pmd_value |= PMD_SECT_S; - } + if (cachepolicy != CPOLICY_WRITEALLOC) { + pr_warn("Forcing write-allocate cache policy for Armada 370\n"); + cachepolicy = CPOLICY_WRITEALLOC;
Re: armada 370 L2 cache November 14, 2020 04:56PM |
Registered: 6 years ago Posts: 258 |
Quote
Aurora cache disabled: 42 MB/s
Aurora cache enabled: 82 MB/s
Aurora cache enabled and CPU coherency enabled: 99 MB/s
Re: armada 370 L2 cache November 14, 2020 05:31PM |
Admin Registered: 14 years ago Posts: 19,306 |
Re: armada 370 L2 cache November 15, 2020 10:52PM |
Registered: 9 years ago Posts: 166 |
root@OpenWrt:/# devmem 0xd0008100 [ 46.565761] 8<--- cut here --- [ 46.568848] Unhandled fault: external abort on non-linefetch (0x1018) at 0xb6f31100 [ 46.576541] pgd = cdebe8d4 [ 46.579259] [b6f31100] *pgd=2d01d831, *pte=d0008383, *ppte=d0008a33 Bus error
// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Device Tree file for Marvell Armada 370 Reference Design board * (RD-88F6710-A1) * * Copied from arch/arm/boot/dts/armada-370-db.dts * * Copyright (C) 2013 Florian Fainelli <florian@openwrt.org> * * Note: this Device Tree assumes that the bootloader has remapped the * internal registers to 0xf1000000 (instead of the default * 0xd0000000). The 0xf1000000 is the default used by the recent, * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier * boards were delivered with an older version of the bootloader that * left internal registers mapped at 0xd0000000. If you are in this * situation, you should either update your bootloader (preferred * solution) or the below Device Tree should be adjusted. */ /dts-v1/; #include <dt-bindings/input/input.h> #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/gpio/gpio.h> #include "armada-370.dtsi" / { model = "RTNAS V3"; compatible = "marvell,armada-370-rtnasv3", "marvell,armada370", "marvell,armada-370-xp"; chosen { stdout-path = "serial0:115200n8"; }; memory@0 { device_type = "memory"; reg = <0x00000000 0x40000000>; /* 1024 MB */ }; soc { ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000 MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000 MBUS_ID(0x09, 0x01) 0 0xf1100000 0x10000>; internal-regs { serial@12000 { status = "okay"; }; sata@a0000 { nr-ports = <2>; status = "okay"; }; mvsdio@d4000 { pinctrl-0 = <&sdio_pins1>; pinctrl-names = "default"; status = "disabled"; /* No CD or WP GPIOs */ broken-cd; }; usb@50000 { status = "okay"; }; usb@51000 { status = "okay"; }; gpio-keys { compatible = "gpio-keys"; pinctrl-0 = <&reset_button_pin &pwr_button_pin>; pinctrl-names = "default"; reset_button { label = "Reset Button"; linux,code = <KEY_RESTART>; gpios = <&gpio1 30 GPIO_ACTIVE_LOW>; }; wps_button { label = "Software Button"; linux,code = <KEY_POWER>; gpios = <&gpio1 20 GPIO_ACTIVE_LOW>; }; }; gpio-leds { compatible = "gpio-leds"; pinctrl-names = "default"; pinctrl-0 = <&pwr_led_pin &wps_led_pins>; blue_pwr_led { label = "rtnasv3:blue:pwr"; gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>; default-state = "keep"; }; blue_wps_led { label = "rtnasv3:blue:wps"; gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>; default-state = "off"; }; }; }; }; }; &mdio { pinctrl-0 = <&mdio_pins>; pinctrl-names = "default"; status = "okay"; switch: switch0@0 { compatible = "marvell,mv88e6085"; #address-cells = <1>; #size-cells = <0>; reg = <0x0>; interrupt-controller; #interrupt-cells = <2>; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; label = "lan1"; }; port@1 { reg = <1>; label = "lan2"; }; port@2 { reg = <2>; label = "lan3"; }; port@3 { reg = <3>; label = "lan4"; }; port@4 { reg = <4>; label = "wan"; }; port@5 { reg = <5>; label = "cpu"; ethernet = <ð1>; fixed-link { speed = <1000>; full-duplex; }; }; }; mdio { #address-cells = <1>; #size-cells = <0>; switchphy0: switchphy@0 { reg = <0>; interrupt-parent = <&switch>; interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; }; switchphy1: switchphy@1 { reg = <1>; interrupt-parent = <&switch>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH>; }; switchphy2: switchphy@2 { reg = <2>; interrupt-parent = <&switch>; interrupts = <2 IRQ_TYPE_LEVEL_HIGH>; }; switchphy3: switchphy@3 { reg = <3>; interrupt-parent = <&switch>; interrupts = <3 IRQ_TYPE_LEVEL_HIGH>; }; switchphy4: switchphy@4 { reg = <4>; interrupt-parent = <&switch>; interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; }; }; }; }; &pciec { status = "okay"; /* Internal mini-PCIe connector */ pcie@1,0 { /* Port 0, Lane 0 */ status = "okay"; }; /* Internal mini-PCIe connector */ pcie@2,0 { /* Port 1, Lane 0 */ status = "okay"; }; }; &pinctrl { compatible = "marvell,mv88f6710-pinctrl"; pwr_button_pin: pwr-button-pin { marvell,pins = "mpp52"; marvell,function = "gpio"; }; reset_button_pin: reset-button-pin { marvell,pins = "mpp62"; marvell,function = "gpio"; }; pwr_led_pin: pwr-led-pin { marvell,pins = "mpp6"; marvell,function = "gpio"; }; wps_led_pins: wps-led-pins { marvell,pins = "mpp50"; marvell,function = "gpio"; }; }; &nand_controller { status = "okay"; nand@0 { reg = <0>; label = "pxa3xx_nand-0"; nand-rb = <0>; marvell,nand-keep-config; nand-on-flash-bbt; nand-ecc-strength = <4>; nand-ecc-step-size = <512>; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "u-boot"; reg = <0x0 0x400000>; }; partition@400000 { label = "uboot_env"; reg = <0x400000 0x400000>; }; partition@800000 { label = "vendor"; reg = <0x800000 0x400000>; }; partition@c00000 { label = "unused"; reg = <0xc00000 0xc00000>; }; partition@1800000 { label = "kernel"; reg = <0x1800000 0x400000>; }; partition@1c00000 { label = "ubi"; reg = <0x1c00000 0x3e400000>; }; partition@40000000 { label = "syscfg"; reg = <0x40000000 0xbbc00000>; }; }; }; }; &coherencyfab { broken-idle; }; ð0 { status = "disabled"; }; /* eth1 is connected to a Marvell 88E6171 switch, without a PHY. So set * fixed speed and duplex. */ ð1 { pinctrl-names = "default"; pinctrl-0 = <&ge1_rgmii_pins>; status = "okay"; phy-mode = "rgmii-id"; fixed-link { speed = <1000>; full-duplex; }; }; &rtc { status = "disabled"; };
Re: armada 370 L2 cache November 15, 2020 11:03PM |
Admin Registered: 14 years ago Posts: 19,306 |
devmem 0xf0008100 devmem 0xf0008104