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Re: WD MyCloud Gen2 (Glacier, Armada 375) February 16, 2026 01:24AM |
Registered: 9 months ago Posts: 9 |
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ygi
Re: WD MyCloud Gen2 (Glacier, Armada 375) February 16, 2026 04:35AM |
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Re: WD MyCloud Gen2 (Glacier, Armada 375) February 17, 2026 01:27AM |
Admin Registered: 15 years ago Posts: 20,119 |
sha256: c6833ad359215ce002c1a249d8641fa58e6e2aae98aacb6062b7583afb23a60e
uboot.2025.10-tld-1.wd-glacier.kwb uboot.2025.10-tld-1.wd-glacier.boot.cmd uboot.2025.10-tld-1.wd-glacier.boot.scr README.txt
kwboot -t -a -B 115200 /dev/ttyUSB0 -b uboot.2025.10-tld-1.wd-glacier.kwbNote: the serial device ttyUSB0 is typical for Debian-based distro. On other distro it might be different (see detailed kwboot example here).
dm tree setenv ipaddr <some valid IP address> ping <your router IP address> mdio list mii info dm tree
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ygi
Re: WD MyCloud Gen2 (Glacier, Armada 375) February 17, 2026 02:26PM |
kwboot -t -a -B 115200 /dev/ttyUSB0 -b Downloads/uboot.2025.10-tld-1.wd-glacier.bodhi.260216/uboot.2025.10-tld-1.wd-glacier.kwb
kwboot version 2026.01
Detected kwbimage v1 with SPI boot signature
Patching image boot signature to UART
Aligning image header to Xmodem block size
Sending boot message. Please reboot the target...\
Sending boot image header (92032 bytes)...
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87 % [......................................................................]
97 % [................... ]
Done
General initialization - Version: 1.0.0
High speed PHY - Version: 0.1.1 (COM-PHY-V20)
USB2 UTMI PHY initialized succesfully
USB2 UTMI PHY initialized succesfully
High speed PHY - Ended Successfully
DDR3 Training Sequence - Ver 5.7.1
DDR3 Training Sequence - Run with PBS.
DDR3 Training Sequence - Ended Successfully
Sending boot image data (502372 bytes)...
0 % [......................................................................]
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Done
Finishing transfer
[Type Ctrl-\ + c to quit]
U-Boot 2025.10-tld-1 (Feb 16 2026 - 23:03:59 -0800)
Western Digital MyCloud Gen2 (Glacier)
SoC: MV88F6720-A0 at 800 MHz
Model: WD MyCloud Gen2
DRAM: 512 MiB (534 MHz, 16-bit, ECC not enabled)
Core: 28 devices, 19 uclasses, devicetree: separate
MMC:
Loading Environment from nowhere... OK
Model: WD MyCloud Gen2
Net:
Warning: mvpp2-0 (eth0) using random MAC address - 42:55:4a:c6:2b:cb
eth0: mvpp2-0
Hit any key to stop autoboot: 0
WD-Glacier> dm tree
Class Seq Probed Driver Name
-----------------------------------------------------------
root 0 [ + ] root_driver root_driver
simple_bus 0 [ + ] simple_bus |-- soc
simple_bus 1 [ + ] simple_bus | `-- internal-regs
mdio 0 [ + ] mvmdio | |-- mdio@c0054
eth_phy_ge 0 [ + ] eth_phy_generic_drv | | `-- ethernet-phy@0
misc 0 [ + ] mvpp2_base | |-- ethernet@f0000
ethernet 0 [ + ] mvpp2 | | `-- mvpp2-0
bootdev 0 [ ] eth_bootdev | | `-- mvpp2-0.bootdev
rtc 0 [ ] rtc-mv | |-- rtc@10300
spi 0 [ ] mvebu_spi | |-- spi@10600
spi_flash 0 [ ] jedec_spi_nor | | `-- spi-flash@0
i2c 0 [ ] i2c_mvtwsi | |-- i2c@11000
i2c 1 [ ] i2c_mvtwsi | |-- i2c@11100
serial 0 [ + ] ns16550_serial | |-- serial@12000
gpio 0 [ ] gpio_mvebu | |-- gpio@18100
gpio 1 [ ] gpio_mvebu | |-- gpio@18140
gpio 2 [ ] gpio_mvebu | |-- gpio@18180
syscon 0 [ ] mvebu-system-control | |-- system-controller@18200
reset 0 [ ] mvebu-reset | | `-- mvebu-reset
timer 0 [ + ] orion_timer | |-- timer@20300
usb 0 [ ] ehci_mvebu | |-- usb@54000
usb 1 [ ] xhci_mvebu | |-- usb@58000
ahci 0 [ ] sata_mv_ahci | `-- sata@a0000
bootstd 0 [ ] bootstd_drv |-- bootstd
bootmeth 0 [ ] bootmeth_extlinux | |-- extlinux
bootmeth 1 [ ] bootmeth_script | |-- script
bootmeth 2 [ ] bootmeth_efi_mgr | |-- efi_mgr
bootmeth 3 [ ] bootmeth_efi | |-- efi
bootmeth 4 [ ] bootmeth_pxe | `-- pxe
efi 0 [ ] EFI block driver `-- efi
WD-Glacier> setenv ipaddr 10.0.0.115
WD-Glacier> ping 10.0.0.101
Could not get PHY for mdio@c0054: addr 0
mvpp2 mvpp2-0: cannot connect to phy
Using mvpp2-0 device
ARP Retry count exceeded; starting again
ping failed; host 10.0.0.101 is not alive
WD-Glacier> ping 10.0.0.125
Could not get PHY for mdio@c0054: addr 0
mvpp2 mvpp2-0: cannot connect to phy
Using mvpp2-0 device
ARP Retry count exceeded; starting again
ping failed; host 10.0.0.125 is not alive
WD-Glacier> ping 10.0.0.126
Could not get PHY for mdio@c0054: addr 0
mvpp2 mvpp2-0: cannot connect to phy
Using mvpp2-0 device
ARP Retry count exceeded; starting again
ping failed; host 10.0.0.126 is not alive
WD-Glacier> setenv netmask 255.255.255.224
WD-Glacier> printenv
arch=arm
baudrate=115200
board=wd-glacier
board_name=wd-glacier
bootcmd=bootflow scan -lb
bootdelay=10
console=ttyS0,115200
cpu=armv7
ethact=mvpp2-0
ethaddr=42:55:4a:c6:2b:cb
fdt_addr_r=0x2000000
fdt_high=0x10000000
fdtcontroladdr=1fb69750
fdtfile=armada-375-wd-mycloud-gen2.dtb
initrd_high=0x10000000
ipaddr=10.0.0.115
kernel_addr_r=0x1000000
loadaddr=0x800000
mtdparts=mtdparts=spi0.0:1m(u-boot)
netmask=255.255.255.224
pxefile_addr_r=0x1900000
ramdisk_addr_r=0x2200000
scriptaddr=0x1800000
soc=mvebu
stderr=serial@12000
stdin=serial@12000
stdout=serial@12000
vendor=western-digital
ver=U-Boot 2025.10-tld-1 (Feb 16 2026 - 23:03:59 -0800)\
Western Digital MyCloud Gen2 (Glacier)
Environment size: 682/65532 bytes
WD-Glacier> ping 10.0.0.125
Could not get PHY for mdio@c0054: addr 0
mvpp2 mvpp2-0: cannot connect to phy
Using mvpp2-0 device
ARP Retry count exceeded; starting again
ping failed; host 10.0.0.125 is not alive
WD-Glacier> mii info
WD-Glacier> mdio list
mdio@c0054:
WD-Glacier> sata info
Device 0: Model: WDC WD20EFRX-68EUZN0 Firm: 82.00A82 Ser#: WD-WCC4M7ZE3VZ9
Type: Hard Disk
Supports 48-bit addressing
Capacity: 1907729.0 MB = 1863.0 GB (3907029168 x 512)
WD-Glacier> usb start
starting USB...
USB EHCI 1.00
MVEBU XHCI INIT controller @ 0xf105b880
Register 2000120 NbrPorts 2
Starting the controller
USB XHCI 1.00
cannot reset port 1!?
Bus usb@54000: 1 USB Device(s) found
Bus usb@58000: 2 USB Device(s) found
scanning usb for storage devices... 1 Storage Device(s) found
WD-Glacier> usb info
1: Hub, USB Revision 2.0
- u-boot EHCI Host Controller
- Class: Hub
- PacketSize: 64 Configurations: 1
- Vendor: 0x0000 Product 0x0000 Version 1.0
Configuration: 1
- Interfaces: 1 Self Powered 0mA
Interface: 0
- Alternate Setting 0, Endpoints: 1
- Class Hub
- Endpoint 1 In Interrupt MaxPacket 8 Interval 255ms
1: Hub, USB Revision 3.0
- U-Boot XHCI Host Controller
- Class: Hub
- PacketSize: 512 Configurations: 1
- Vendor: 0x0000 Product 0x0000 Version 1.0
Configuration: 1
- Interfaces: 1 Self Powered 0mA
Interface: 0
- Alternate Setting 0, Endpoints: 1
- Class Hub
- Endpoint 1 In Interrupt MaxPacket 8 Interval 255ms
2: Mass Storage, USB Revision 3.0
- PNY PNY 2.5in drive enclosure 15012902765
- Class: (from Interface) Mass Storage
- PacketSize: 512 Configurations: 1
- Vendor: 0x154b Product 0x5678 Version 84.8
Configuration: 1
- Interfaces: 1 Bus Powered 24mA
Interface: 0
- Alternate Setting 0, Endpoints: 2
- Class Mass Storage, Transp. SCSI, Bulk only
- String: "SATA"
- Endpoint 1 In Bulk MaxPacket 1024
- Endpoint 2 Out Bulk MaxPacket 1024
WD-Glacier> dm tree
Class Seq Probed Driver Name
-----------------------------------------------------------
root 0 [ + ] root_driver root_driver
simple_bus 0 [ + ] simple_bus |-- soc
simple_bus 1 [ + ] simple_bus | `-- internal-regs
mdio 0 [ + ] mvmdio | |-- mdio@c0054
eth_phy_ge 0 [ + ] eth_phy_generic_drv | | `-- ethernet-phy@0
misc 0 [ + ] mvpp2_base | |-- ethernet@f0000
ethernet 0 [ + ] mvpp2 | | `-- mvpp2-0
bootdev 0 [ ] eth_bootdev | | `-- mvpp2-0.bootdev
rtc 0 [ ] rtc-mv | |-- rtc@10300
spi 0 [ ] mvebu_spi | |-- spi@10600
spi_flash 0 [ ] jedec_spi_nor | | `-- spi-flash@0
i2c 0 [ ] i2c_mvtwsi | |-- i2c@11000
i2c 1 [ ] i2c_mvtwsi | |-- i2c@11100
serial 0 [ + ] ns16550_serial | |-- serial@12000
gpio 0 [ ] gpio_mvebu | |-- gpio@18100
gpio 1 [ ] gpio_mvebu | |-- gpio@18140
gpio 2 [ ] gpio_mvebu | |-- gpio@18180
syscon 0 [ ] mvebu-system-control | |-- system-controller@18200
reset 0 [ ] mvebu-reset | | `-- mvebu-reset
timer 0 [ + ] orion_timer | |-- timer@20300
usb 0 [ + ] ehci_mvebu | |-- usb@54000
usb_hub 0 [ + ] usb_hub | | `-- usb_hub
usb 1 [ + ] xhci_mvebu | |-- usb@58000
usb_hub 1 [ + ] usb_hub | | `-- usb_hub
usb_mass_s 0 [ + ] usb_mass_storage | | `-- usb_mass_storage
blk 1 [ + ] usb_storage_blk | | |-- usb_mass_storage.lun0
partition 3 [ + ] blk_partition | | | `-- usb_mass_storage.lun0:1
bootdev 2 [ ] usb_bootdev | | `-- usb_mass_storage.lun0.bootdev
ahci 0 [ + ] sata_mv_ahci | `-- sata@a0000
blk 0 [ + ] sata_mv_blk | |-- sata@a0000.blk
partition 0 [ + ] blk_partition | | |-- sata@a0000.blk:1
partition 1 [ + ] blk_partition | | |-- sata@a0000.blk:2
partition 2 [ + ] blk_partition | | `-- sata@a0000.blk:3
bootdev 1 [ ] sata_bootdev | `-- sata@a0000.bootdev
bootstd 0 [ ] bootstd_drv |-- bootstd
bootmeth 0 [ ] bootmeth_extlinux | |-- extlinux
bootmeth 1 [ ] bootmeth_script | |-- script
bootmeth 2 [ ] bootmeth_efi_mgr | |-- efi_mgr
bootmeth 3 [ ] bootmeth_efi | |-- efi
bootmeth 4 [ ] bootmeth_pxe | `-- pxe
efi 0 [ ] EFI block driver `-- efi
[ 89.209179] mvpp2 f10f0000.ethernet eth0: could not attach PHY (-19)still came back to bite me. I read somewhere that extracting the .dtb from the running kernel gets you the active state as seen by the OS, not the .dtb that's been baked into the kernel. So I pulled the .dtb from the broken uboot and the one from the working stock uboot. Next is decompilling the two and see if something's obviously different in the way the ethernet port is configured. TBH, I have no idea if I'm onto something or just going on a wild goose chase.
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Re: WD MyCloud Gen2 (Glacier, Armada 375) February 17, 2026 04:01PM |
Admin Registered: 15 years ago Posts: 20,119 |
> U-Boot 2025.10-tld-1 (Feb 16 2026 - 23:03:59 > -0800) > Western Digital MyCloud Gen2 (Glacier)
> Net: > Warning: mvpp2-0 (eth0) using random MAC address - > 42:55:4a:c6:2b:cb > eth0: mvpp2-0 > Hit any key to stop autoboot: 0 > mdio 0 [ + ] mvmdio | > |-- mdio@c0054 > eth_phy_ge 0 [ + ] eth_phy_generic_drv | > | `-- ethernet-phy@0 > misc 0 [ + ] mvpp2_base | > |-- ethernet@f0000 > ethernet 0 [ + ] mvpp2 | > | `-- mvpp2-0 > bootdev 0 [ ] eth_bootdev | > | `-- mvpp2-0.bootdevNot bad, means the correct driver is running.
> WD-Glacier> ping 10.0.0.101 > Could not get PHY for mdio@c0054: addr 0 > mvpp2 mvpp2-0: cannot connect to phy > Using mvpp2-0 deviceThis is where it's different from the DS215j. This is a generic PHY. While the DS215j has Marvell PHY, and it is identied as such and has no problem connecting to the PHY. The DS215j is also has Ethernet problem, though.
> WD-Glacier> setenv netmask 255.255.255.224This netmask only good to broadcast. The ping command is direct, so IP address is all you'll need.
dmesg ls -l /proc/device-tree/
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ygi
Re: WD MyCloud Gen2 (Glacier, Armada 375) February 18, 2026 05:37PM |
&pinctrl {
sata_sd_pins: sata-sd-pins {
marvell,pins = "mpp63", "mpp66";
marvell,function = "gpio";
};
sdio_st_pins: sdio-st-pins {
marvell,pins = "mpp44", "mpp45";
marvell,function = "gpio";
};
};
&sata {
status = "okay";
nr-ports = <2>;
pinctrl-0 = <&sata_sd_pins>;
pinctrl-names = "default";
sd-gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>, <&gpio2 2 GPIO_ACTIVE_HIGH>;
};
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Re: WD MyCloud Gen2 (Glacier, Armada 375) February 19, 2026 03:26AM |
Admin Registered: 15 years ago Posts: 20,119 |
md.l f1018000 8 md.l f1018100 1 md.l f1018140 1And then try spin up the HDD
scsi resetIf scsi command works and the HDD initialized, repeat the dump
md.l f1018100 1 md.l f1018140 1
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ygi
Re: WD MyCloud Gen2 (Glacier, Armada 375) February 19, 2026 05:33AM |
model = "WD My Cloud Gen2: Marvell Armada 375";at the top of the file, I would assume that's the file they use when they build their stock kernel. I'm not running that though.
BootROM - 1.51
Booting from SPI flash
General initialization - Version: 1.0.0
High speed PHY - Version: 0.1.1 (COM-PHY-V20)
USB2 UTMI PHY initialized succesfully
USB2 UTMI PHY initialized succesfully
High speed PHY - Ended Successfully
DDR3 Training Sequence - Ver 5.7.1
DDR3 Training Sequence - Run with PBS.
DDR3 Training Sequence - Ended Successfully
BootROM: Image checksum verification PASSED
** LOADER **
U-Boot 2013.01_v1.03 (Nov 20 2014 - 16:39:45) Marvell version: 2014_T2.0p3
Board: WD_Glacier_DB-88F6720-V2
SoC: MV88F6720 Rev A0
running 2 CPUs
CPU: ARM Cortex A9 MPCore (Rev 1) LE
CPU 0
CPU @ 800 [MHz]
L2 @ 400 [MHz]
TClock @ 200 [MHz]
DDR @ 534 [MHz]
DDR 16Bit Width, FastPath Memory Access, DLB Enabled
DRAM: 512 MiB
Map: Code: 0x1fed6000:0x1ff92c90
BSS: 0x1ffefa20
Stack: 0x1f9c5f20
Heap: 0x1f9c6000:0x1fed6000
SF: Detected MX25L8006E with page size 64 KiB, total 1 MiB
*** Warning - bad CRC, using default environment
PCI-e 0: Detected No Link.
PCI-e 1: Detected No Link.
SF: Detected MX25L8006E with page size 64 KiB, total 1 MiB
MAC addr: 00:14:EE:06:43:3B
### Loading Firmware from USB 3.0 Disk ###
USB2.0 0: Host Mode
USB2.0 1: Device Mode
USB3.0 0: Host Mode
Board configuration detected:
GE-PHY-0 on MAC0
SERDES configuration:
Lane #0: PCIe0
Lane #1: PCIe1
Lane #2: SATA0
Lane #3: USB3
Net: egiga0 [PRIME]
*** ERROR: ping address not given
Hit any key to stop autoboot: 0
Marvell>> md.l f1018000 8
f1018000: 00020020 00000022 00000022 00000000 ..."...".......
f1018010: 04400000 00000000 00000000 00004000 ..@..........@..
Marvell>> md.l f1018100 1
f1018100: 00400000 ..@.
Marvell>> md.l f1018140 1
f1018140: 04001000 ....
Marvell>> scsi reset
Reset SCSI
MV94XX controller not present
Marvell>> ide reset
Reset IDE:
Marvell Serial ATA Adapter
Integrated Sata device found
Device 0 @ 0 0:
Model: WDC WD20EFRX-68EUZN0 Firm: 82.00A82 Ser#: WD-WCC4M7ZE3VZ9
Type: Hard Disk
Supports 48-bit addressing
Capacity: 1907729.0 MB = 1863.0 GB (3907029168 x 512)
Marvell>> md.l f1018000 8
f1018000: 00020020 00000022 00000022 00000000 ..."...".......
f1018010: 04400000 00000000 00000000 00004000 ..@..........@..
Marvell>> md.l f1018100 1
f1018100: 00400000 ..@.
Marvell>> md.l f1018140 1
f1018140: 04001000 ....
Marvell>>
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Re: WD MyCloud Gen2 (Glacier, Armada 375) February 19, 2026 12:19PM |
Admin Registered: 15 years ago Posts: 20,119 |
> model = "WD My Cloud Gen2: Marvell Armada > 375";at the top of the file, I would
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ygi
Re: WD MyCloud Gen2 (Glacier, Armada 375) February 20, 2026 07:36AM |
/*
* Device Tree file for Marvell Armada 375 evaluation board
* (DB-88F6720)
*
* Copyright (C) 2014 Marvell
*
* Gregory CLEMENT <gregory.clement@free-electrons.com>
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include "armada-375.dtsi"
/ {
model = "WD My Cloud Gen2: Marvell Armada 375";
compatible = "marvell,a375-db", "marvell,armada375";
chosen {
stdout-path = "serial0:115200n8";
};
memory@0 {
device_type = "memory";
reg = <0x00000000 0x20000000>; /* 1/2 GB */
};
soc {
ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000 /* internal regs */
MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000 /* bootrom */
MBUS_ID(0x09, 0x09) 0 0xf1100000 0x10000 /* CESA0: PHYS=0xf1100000 size 64K */
MBUS_ID(0x09, 0x05) 0 0xf1110000 0x10000>; /* CESA1: PHYS=0xf1110000 size 64K */
};
gpio-leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&sys_led_pins>;
system-red {
label = "system-red";
gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>; // chip, pin, state (1=active-low)
// Triggers: none nand-disk timer oneshot heartbeat backlight gpio cpu0 cpu1 default-on
linux,default-trigger = "default-on";
default-state = "on";
};
system-green {
label = "system-green";
gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>; // 43 (mpp43) - 32 (gpio in chip) = 11 (pin in this chip)
linux,default-trigger = "default-on";
default-state = "on";
};
system-blue {
label = "system-blue";
gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "default-off";
default-state = "off";
};
};
usb3_phy_gpio: usb3-phy-gpio {
compatible = "usb-nop-xceiv";
vcc-supply = <®_usb3_vbus_gpio>;
};
reg_usb3_vbus_gpio: usb3-vbus-gpio {
compatible = "mv,vbus-regulator";
pinctrl-names = "default";
pinctrl-0 = <&xhci0_vbus_pins>;
regulator-name = "xhci0-vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
regulator-always-on;
gpio = <&gpio0 13 GPIO_ACTIVE_LOW>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
};
&pciec {
status = "okay";
};
/*
* The two PCIe units are accessible through
* standard PCIe slots on the board.
*/
&pcie0 {
/* Port 0, Lane 0 */
status = "disabled";
};
&pcie1 {
/* Port 1, Lane 0 */
status = "disabled";
};
&spi0 {
pinctrl-0 = <&spi0_pins>;
pinctrl-names = "default";
status = "okay";
spi-flash@0 {
#address-cells = <1>;
#size-cells = <1>;
/* MX25L8006E */
compatible = "mxicy,mx25l8005", "jedec,spi-nor";
reg = <0>; /* Chip select 0 */
spi-max-frequency = <108000000>;
partition@0 {
label = "u-boot";
reg = <0x0 0x100000>;
};
};
};
&uart0 {
status = "okay";
};
&pinctrl {
sata_sd_pins: sata-sd-pins {
marvell,pins = "mpp63", "mpp66";
marvell,function = "gpio";
};
sys_led_pins: sys-led-pins {
marvell,pins = "mpp20", "mpp43", "mpp22"; // R G B
marvell,function = "gpio";
};
sdio_st_pins: sdio-st-pins {
marvell,pins = "mpp44", "mpp45";
marvell,function = "gpio";
};
xhci0_vbus_pins: xhci0-vbus-pins {
marvell,pins = "mpp13";
marvell,function = "gpio";
};
};
&sata {
status = "okay";
nr-ports = <2>;
pinctrl-0 = <&sata_sd_pins>;
pinctrl-names = "default";
sd-gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>, <&gpio2 2 GPIO_ACTIVE_HIGH>;
};
&usb1 {
status = "okay";
};
&usb2 {
status = "okay";
};
&mdio {
phy0: ethernet-phy@0 {
reg = <0>;
};
// phy3: ethernet-phy@3 {
// reg = <3>;
// };
};
ðernet {
status = "okay";
};
ð0 {
status = "okay";
phy = <&phy0>;
phy-mode = "rgmii-id";
};
/*
* Device Tree Include file for Marvell Armada 375 family SoC
*
* Copyright (C) 2014 Marvell
*
* Gregory CLEMENT <gregory.clement@free-electrons.com>
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/phy/phy.h>
#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
/ {
#address-cells = <1>;
#size-cells = <1>;
model = "Marvell Armada 375 family SoC";
compatible = "marvell,armada375";
aliases {
gpio0 = &gpio0;
gpio1 = &gpio1;
gpio2 = &gpio2;
serial0 = &uart0;
serial1 = &uart1;
};
clocks {
/* 1 GHz fixed main PLL */
mainpll: mainpll {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <1000000000>;
};
/* 25 MHz reference crystal */
refclk: oscillator {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
};
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
enable-method = "marvell,armada-375-smp";
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <0>;
};
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <1>;
};
};
pmu {
compatible = "arm,cortex-a9-pmu";
interrupts-extended = <&mpic 3>;
};
soc {
compatible = "marvell,armada375-mbus", "simple-bus";
#address-cells = <2>;
#size-cells = <1>;
controller = <&mbusc>;
interrupt-parent = <&gic>;
pcie-mem-aperture = <0xe0000000 0x8000000>;
pcie-io-aperture = <0xe8000000 0x100000>;
bootrom {
compatible = "marvell,bootrom";
reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
};
devbus_bootcs: devbus-bootcs {
compatible = "marvell,mvebu-devbus";
reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
#address-cells = <1>;
#size-cells = <1>;
clocks = <&coreclk 0>;
status = "disabled";
};
devbus_cs0: devbus-cs0 {
compatible = "marvell,mvebu-devbus";
reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
#address-cells = <1>;
#size-cells = <1>;
clocks = <&coreclk 0>;
status = "disabled";
};
devbus_cs1: devbus-cs1 {
compatible = "marvell,mvebu-devbus";
reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>;
#address-cells = <1>;
#size-cells = <1>;
clocks = <&coreclk 0>;
status = "disabled";
};
devbus_cs2: devbus-cs2 {
compatible = "marvell,mvebu-devbus";
reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>;
ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>;
#address-cells = <1>;
#size-cells = <1>;
clocks = <&coreclk 0>;
status = "disabled";
};
devbus_cs3: devbus-cs3 {
compatible = "marvell,mvebu-devbus";
reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>;
ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>;
#address-cells = <1>;
#size-cells = <1>;
clocks = <&coreclk 0>;
status = "disabled";
};
internal-regs {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
L2: cache-controller@8000 {
compatible = "arm,pl310-cache";
reg = <0x8000 0x1000>;
cache-unified;
cache-level = <2>;
arm,double-linefill-incr = <0>;
arm,double-linefill-wrap = <0>;
arm,double-linefill = <0>;
prefetch-data = <1>;
};
scu: scu@c000 {
compatible = "arm,cortex-a9-scu";
reg = <0xc000 0x58>;
};
timer0: timer@c600 {
compatible = "arm,cortex-a9-twd-timer";
reg = <0xc600 0x20>;
interrupts = <GIC_PPI 13 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>;
clocks = <&coreclk 2>;
};
gic: interrupt-controller@d000 {
compatible = "arm,cortex-a9-gic";
#interrupt-cells = <3>;
#size-cells = <0>;
interrupt-controller;
reg = <0xd000 0x1000>,
<0xc100 0x100>;
};
mdio: mdio@c0054 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "marvell,orion-mdio";
reg = <0xc0054 0x4>;
clocks = <&gateclk 19>;
};
/* Network controller */
ethernet: ethernet@f0000 {
compatible = "marvell,armada-375-pp2";
reg = <0xf0000 0xa000>, /* Packet Processor regs */
<0xc0000 0x3060>, /* LMS regs */
<0xc4000 0x100>, /* eth0 regs */
<0xc5000 0x100>; /* eth1 regs */
clocks = <&gateclk 3>, <&gateclk 19>;
clock-names = "pp_clk", "gop_clk";
status = "disabled";
eth0: eth0 {
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
port-id = <0>;
status = "disabled";
};
eth1: eth1 {
interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
port-id = <1>;
status = "disabled";
};
};
rtc: rtc@10300 {
compatible = "marvell,orion-rtc";
reg = <0x10300 0x20>;
interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
};
spi0: spi@10600 {
compatible = "marvell,armada-375-spi",
"marvell,orion-spi";
reg = <0x10600 0x50>;
#address-cells = <1>;
#size-cells = <0>;
cell-index = <0>;
interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&coreclk 0>;
status = "disabled";
};
spi1: spi@10680 {
compatible = "marvell,armada-375-spi",
"marvell,orion-spi";
reg = <0x10680 0x50>;
#address-cells = <1>;
#size-cells = <0>;
cell-index = <1>;
interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&coreclk 0>;
status = "disabled";
};
i2c0: i2c@11000 {
compatible = "marvell,mv64xxx-i2c";
reg = <0x11000 0x20>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
timeout-ms = <1000>;
clocks = <&coreclk 0>;
status = "disabled";
};
i2c1: i2c@11100 {
compatible = "marvell,mv64xxx-i2c";
reg = <0x11100 0x20>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
timeout-ms = <1000>;
clocks = <&coreclk 0>;
status = "disabled";
};
uart0: serial@12000 {
compatible = "snps,dw-apb-uart";
reg = <0x12000 0x100>;
reg-shift = <2>;
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
reg-io-width = <1>;
clocks = <&coreclk 0>;
status = "disabled";
};
uart1: serial@12100 {
compatible = "snps,dw-apb-uart";
reg = <0x12100 0x100>;
reg-shift = <2>;
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
reg-io-width = <1>;
clocks = <&coreclk 0>;
status = "disabled";
};
pinctrl: pinctrl@18000 {
compatible = "marvell,mv88f6720-pinctrl";
reg = <0x18000 0x24>;
i2c0_pins: i2c0-pins {
marvell,pins = "mpp14", "mpp15";
marvell,function = "i2c0";
};
i2c1_pins: i2c1-pins {
marvell,pins = "mpp61", "mpp62";
marvell,function = "i2c1";
};
nand_pins: nand-pins {
marvell,pins = "mpp0", "mpp1", "mpp2",
"mpp3", "mpp4", "mpp5",
"mpp6", "mpp7", "mpp8",
"mpp9", "mpp10", "mpp11",
"mpp12", "mpp13";
marvell,function = "nand";
};
sdio_pins: sdio-pins {
marvell,pins = "mpp24", "mpp25", "mpp26",
"mpp27", "mpp28", "mpp29";
marvell,function = "sd";
};
spi0_pins: spi0-pins {
marvell,pins = "mpp0", "mpp1", "mpp4",
"mpp5", "mpp8", "mpp9";
marvell,function = "spi0";
};
};
gpio0: gpio@18100 {
compatible = "marvell,orion-gpio";
reg = <0x18100 0x40>;
ngpios = <32>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
};
gpio1: gpio@18140 {
compatible = "marvell,orion-gpio";
reg = <0x18140 0x40>;
ngpios = <32>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
};
gpio2: gpio@18180 {
compatible = "marvell,orion-gpio";
reg = <0x18180 0x40>;
ngpios = <3>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
};
systemc: system-controller@18200 {
compatible = "marvell,armada-375-system-controller";
reg = <0x18200 0x100>;
};
gateclk: clock-gating-control@18220 {
compatible = "marvell,armada-375-gating-clock";
reg = <0x18220 0x4>;
clocks = <&coreclk 0>;
#clock-cells = <1>;
};
usbcluster: usb-cluster@18400 {
compatible = "marvell,armada-375-usb-cluster";
reg = <0x18400 0x4>;
#phy-cells = <1>;
};
mbusc: mbus-controller@20000 {
compatible = "marvell,mbus-controller";
reg = <0x20000 0x100>, <0x20180 0x20>;
};
mpic: interrupt-controller@20a00 {
compatible = "marvell,mpic";
reg = <0x20a00 0x2d0>, <0x21070 0x58>;
#interrupt-cells = <1>;
#size-cells = <1>;
interrupt-controller;
msi-controller;
interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
};
timer1: timer@20300 {
compatible = "marvell,armada-375-timer", "marvell,armada-370-timer";
reg = <0x20300 0x30>, <0x21040 0x30>;
interrupts-extended = <&gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
<&mpic 5>,
<&mpic 6>;
clocks = <&coreclk 0>, <&refclk>;
clock-names = "nbclk", "fixed";
};
watchdog: watchdog@20300 {
compatible = "marvell,armada-375-wdt";
reg = <0x20300 0x34>, <0x20704 0x4>, <0x18254 0x4>;
clocks = <&coreclk 0>, <&refclk>;
clock-names = "nbclk", "fixed";
};
cpurst: cpurst@20800 {
compatible = "marvell,armada-370-cpu-reset";
reg = <0x20800 0x10>;
};
coherencyfab: coherency-fabric@21010 {
compatible = "marvell,armada-375-coherency-fabric";
reg = <0x21010 0x1c>;
};
usb0: usb@50000 {
compatible = "marvell,orion-ehci";
reg = <0x50000 0x500>;
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gateclk 18>;
phys = <&usbcluster PHY_TYPE_USB2>;
phy-names = "usb";
status = "disabled";
};
usb1: usb@54000 {
compatible = "marvell,orion-ehci";
reg = <0x54000 0x500>;
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gateclk 26>;
status = "disabled";
};
usb2: usb3@58000 {
compatible = "marvell,armada-375-xhci";
reg = <0x58000 0x20000>,<0x5b880 0x80>;
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gateclk 16>;
phys = <&usbcluster PHY_TYPE_USB3>;
phy-names = "usb";
status = "disabled";
};
xor0: xor@60800 {
compatible = "marvell,orion-xor";
reg = <0x60800 0x100
0x60A00 0x100>;
clocks = <&gateclk 22>;
status = "okay";
xor00 {
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
dmacap,memcpy;
dmacap,xor;
};
xor01 {
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
dmacap,memcpy;
dmacap,xor;
dmacap,memset;
};
};
xor1: xor@60900 {
compatible = "marvell,orion-xor";
reg = <0x60900 0x100
0x60b00 0x100>;
clocks = <&gateclk 23>;
status = "okay";
xor10 {
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
dmacap,memcpy;
dmacap,xor;
};
xor11 {
interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
dmacap,memcpy;
dmacap,xor;
dmacap,memset;
};
};
cesa: crypto@90000 {
compatible = "marvell,armada-375-crypto";
reg = <0x90000 0x10000>;
reg-names = "regs";
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gateclk 30>, <&gateclk 31>,
<&gateclk 28>, <&gateclk 29>;
clock-names = "cesa0", "cesa1",
"cesaz0", "cesaz1";
marvell,crypto-srams = <&crypto_sram0>,
<&crypto_sram1>;
marvell,crypto-sram-size = <0x800>;
};
sata: sata@a0000 {
compatible = "marvell,armada-370-sata";
reg = <0xa0000 0x5000>;
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gateclk 14>, <&gateclk 20>;
clock-names = "0", "1";
status = "disabled";
};
nand: nand@d0000 {
compatible = "marvell,armada370-nand";
reg = <0xd0000 0x54>;
#address-cells = <1>;
#size-cells = <1>;
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gateclk 11>;
status = "disabled";
};
sdio: mvsdio@d4000 {
compatible = "marvell,orion-sdio";
reg = <0xd4000 0x200>;
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gateclk 17>;
bus-width = <4>;
cap-sdio-irq;
cap-sd-highspeed;
cap-mmc-highspeed;
status = "disabled";
};
thermal: thermal@e8078 {
compatible = "marvell,armada375-thermal";
reg = <0xe8078 0x4>, <0xe807c 0x8>;
status = "okay";
};
coreclk: mvebu-sar@e8204 {
compatible = "marvell,armada-375-core-clock";
reg = <0xe8204 0x04>;
#clock-cells = <1>;
};
coredivclk: corediv-clock@e8250 {
compatible = "marvell,armada-375-corediv-clock";
reg = <0xe8250 0xc>;
#clock-cells = <1>;
clocks = <&mainpll>;
clock-output-names = "nand";
};
};
pciec: pcie@82000000 {
compatible = "marvell,armada-370-pcie";
status = "disabled";
device_type = "pci";
#address-cells = <3>;
#size-cells = <2>;
msi-parent = <&mpic>;
bus-range = <0x00 0xff>;
ranges =
<0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000
0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0 MEM */
0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0 IO */
0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 1 MEM */
0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 1 IO */>;
pcie0: pcie@1,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
reg = <0x0800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
0x81000000 0 0 0x81000000 0x1 0 1 0>;
bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
marvell,pcie-port = <0>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 5>;
status = "disabled";
};
pcie1: pcie@2,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
reg = <0x1000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
0x81000000 0 0 0x81000000 0x2 0 1 0>;
bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
marvell,pcie-port = <0>;
marvell,pcie-lane = <1>;
clocks = <&gateclk 6>;
status = "disabled";
};
};
crypto_sram0: sa-sram0 {
compatible = "mmio-sram";
reg = <MBUS_ID(0x09, 0x09) 0 0x800>;
clocks = <&gateclk 30>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 MBUS_ID(0x09, 0x09) 0 0x800>;
};
crypto_sram1: sa-sram1 {
compatible = "mmio-sram";
reg = <MBUS_ID(0x09, 0x05) 0 0x800>;
clocks = <&gateclk 31>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 MBUS_ID(0x09, 0x05) 0 0x800>;
};
};
};
|
Re: WD MyCloud Gen2 (Glacier, Armada 375) February 20, 2026 03:38PM |
Admin Registered: 15 years ago Posts: 20,119 |
|
Re: WD MyCloud Gen2 (Glacier, Armada 375) February 23, 2026 03:51PM |
Admin Registered: 15 years ago Posts: 20,119 |
sha256: 5efe88406f054b6697e81c4639d383e8919e0cc5ea5c9c5513daf6ac0874054b
uboot.2026.01-tld-1.wd-glacier.kwb uboot.2025.10-tld-1.wd-glacier.boot.cmd uboot.2025.10-tld-1.wd-glacier.boot.scr README.txt
kwboot -t -a -B 115200 /dev/ttyUSB0 -b uboot.2026.01-tld-1.wd-glacier.kwbNote: the serial device ttyUSB0 is typical for Debian-based distro. On other distro it might be different (see detailed kwboot example here).
dm tree setenv ipaddr <some valid IP address> ping <your router IP address> mdio list mii info sata init sata part dm tree
|
ygi
Re: WD MyCloud Gen2 (Glacier, Armada 375) February 24, 2026 10:49AM |
kwboot -t -a -B 115200 /dev/ttyUSB0 -b Downloads/uboot.2026.01-tld-1.wd-glacier.bodhi.260223/uboot.2026.01-tld-1.wd-glacier.kwb kwboot version 2026.01 Detected kwbimage v1 with SPI boot signature Patching image boot signature to UART Aligning image header to Xmodem block size Sending boot message. Please reboot the target...- Sending boot image header (92032 bytes)... 0 % [......................................................................] 9 % [......................................................................] 19 % [......................................................................] 29 % [......................................................................] 39 % [......................................................................] 48 % [......................................................................] 58 % [......................................................................] 68 % [......................................................................] 78 % [......................................................................] 87 % [......................................................................] 97 % [................... ] Done General initialization - Version: 1.0.0 High speed PHY - Version: 0.1.1 (COM-PHY-V20) USB2 UTMI PHY initialized succesfully USB2 UTMI PHY initialized succesfully High speed PHY - Ended Successfully DDR3 Training Sequence - Ver 5.7.1 DDR3 Training Sequence - Run with PBS. DDR3 Training Sequence - Ended Successfully Sending boot image data (502820 bytes)... 0 % [......................................................................] 1 % [......................................................................] 3 % [......................................................................] 5 % [......................................................................] 7 % [......................................................................] 8 % [......................................................................] 10 % [......................................................................] 12 % [......................................................................] 14 % [......................................................................] 16 % [......................................................................] 17 % [......................................................................] 19 % [......................................................................] 21 % [......................................................................] 23 % [......................................................................] 24 % [......................................................................] 26 % [......................................................................] 28 % [......................................................................] 30 % [......................................................................] 32 % [......................................................................] 33 % [......................................................................] 35 % [......................................................................] 37 % [......................................................................] 39 % [......................................................................] 41 % [......................................................................] 42 % [......................................................................] 44 % [......................................................................] 46 % [......................................................................] 48 % [......................................................................] 49 % [......................................................................] 51 % [......................................................................] 53 % [......................................................................] 55 % [......................................................................] 57 % [......................................................................] 58 % [......................................................................] 60 % [......................................................................] 62 % [......................................................................] 64 % [......................................................................] 65 % [......................................................................] 67 % [......................................................................] 69 % [......................................................................] 71 % [......................................................................] 73 % [......................................................................] 74 % [......................................................................] 76 % [......................................................................] 78 % [......................................................................] 80 % [......................................................................] 81 % [......................................................................] 83 % [......................................................................] 85 % [......................................................................] 87 % [......................................................................] 89 % [......................................................................] 90 % [......................................................................] 92 % [......................................................................] 94 % [......................................................................] 96 % [......................................................................] 98 % [......................................................................] 99 % [......... ] Done Finishing transfer [Type Ctrl-\ + c to quit] U-Boot 2026.01-tld-1 (Feb 23 2026 - 13:22:40 -0800) Western Digital MyCloud Gen2 (Glacier) SoC: MV88F6720-A0 at 800 MHz Model: WD MyCloud Gen2 DRAM: 512 MiB (534 MHz, 16-bit, ECC not enabled) Core: 27 devices, 18 uclasses, devicetree: separate MMC: Loading Environment from nowhere... OK Model: WD MyCloud Gen2 Net: Warning: mvpp2-0 (eth0) using random MAC address - 7a:c8:da:a5:ac:98 eth0: mvpp2-0 Hit any key to stop autoboot: 0 WD-Glacier> dm tree Class Seq Probed Driver Name ----------------------------------------------------------- root 0 [ + ] root_driver root_driver simple_bus 0 [ + ] simple_bus |-- soc simple_bus 1 [ + ] simple_bus | `-- internal-regs mdio 0 [ + ] mvmdio | |-- mdio@c0054 eth_phy_ge 0 [ + ] eth_phy_generic_drv | | `-- ethernet-phy@0 misc 0 [ + ] mvpp2_base | |-- ethernet@f0000 ethernet 0 [ + ] mvpp2 | | `-- mvpp2-0 bootdev 0 [ ] eth_bootdev | | `-- mvpp2-0.bootdev spi 0 [ ] mvebu_spi | |-- spi@10600 spi_flash 0 [ ] jedec_spi_nor | | `-- spi-flash@0 i2c 0 [ ] i2c_mvtwsi | |-- i2c@11000 i2c 1 [ ] i2c_mvtwsi | |-- i2c@11100 serial 0 [ + ] ns16550_serial | |-- serial@12000 gpio 0 [ ] gpio_mvebu | |-- gpio@18100 gpio 1 [ ] gpio_mvebu | |-- gpio@18140 gpio 2 [ ] gpio_mvebu | |-- gpio@18180 syscon 0 [ ] mvebu-system-control | |-- system-controller@18200 reset 0 [ ] mvebu-reset | | `-- mvebu-reset timer 0 [ + ] orion_timer | |-- timer@20300 usb 0 [ ] ehci_mvebu | |-- usb@54000 usb 1 [ ] xhci_mvebu | |-- usb@58000 ahci 0 [ ] sata_mv_ahci | `-- sata@a0000 bootstd 0 [ ] bootstd_drv |-- bootstd bootmeth 0 [ ] bootmeth_extlinux | |-- extlinux bootmeth 1 [ ] bootmeth_script | |-- script bootmeth 2 [ ] bootmeth_efi_mgr | |-- efi_mgr bootmeth 3 [ ] bootmeth_efi | |-- efi bootmeth 4 [ ] bootmeth_pxe | `-- pxe efi 0 [ ] EFI block driver `-- efi WD-Glacier> setenv ipaddr 10.0.0.97 WD-Glacier> ping 10.0.0.126 Could not get PHY for mdio@c0054: addr 0 mvpp2 mvpp2-0: cannot connect to phy Using mvpp2-0 device ARP Retry count exceeded; starting again ping failed; host 10.0.0.126 is not alive WD-Glacier> mdio list mdio@c0054: WD-Glacier> mii info WD-Glacier> sata init Err: Failed to identify SATA device 0 WD-Glacier> sata part Failed to wait for completion on port 0 ATA operation timed out Failed to wait for completion on port 0 ATA operation timed out Disk sata@a0000.blk not ready Failed to wait for completion on port 1 ATA operation timed out Failed to wait for completion on port 1 ATA operation timed out Disk sata@a0000.blk not ready no sata partition table available WD-Glacier> dm tree Class Seq Probed Driver Name ----------------------------------------------------------- root 0 [ + ] root_driver root_driver simple_bus 0 [ + ] simple_bus |-- soc simple_bus 1 [ + ] simple_bus | `-- internal-regs mdio 0 [ + ] mvmdio | |-- mdio@c0054 eth_phy_ge 0 [ + ] eth_phy_generic_drv | | `-- ethernet-phy@0 misc 0 [ + ] mvpp2_base | |-- ethernet@f0000 ethernet 0 [ + ] mvpp2 | | `-- mvpp2-0 bootdev 0 [ ] eth_bootdev | | `-- mvpp2-0.bootdev spi 0 [ ] mvebu_spi | |-- spi@10600 spi_flash 0 [ ] jedec_spi_nor | | `-- spi-flash@0 i2c 0 [ ] i2c_mvtwsi | |-- i2c@11000 i2c 1 [ ] i2c_mvtwsi | |-- i2c@11100 serial 0 [ + ] ns16550_serial | |-- serial@12000 gpio 0 [ ] gpio_mvebu | |-- gpio@18100 gpio 1 [ ] gpio_mvebu | |-- gpio@18140 gpio 2 [ ] gpio_mvebu | |-- gpio@18180 syscon 0 [ ] mvebu-system-control | |-- system-controller@18200 reset 0 [ ] mvebu-reset | | `-- mvebu-reset timer 0 [ + ] orion_timer | |-- timer@20300 usb 0 [ ] ehci_mvebu | |-- usb@54000 usb 1 [ ] xhci_mvebu | |-- usb@58000 ahci 0 [ + ] sata_mv_ahci | `-- sata@a0000 blk 0 [ ] sata_mv_blk | |-- sata@a0000.blk bootdev 1 [ ] sata_bootdev | |-- sata@a0000.bootdev blk 1 [ ] sata_mv_blk | `-- sata@a0000.blk bootstd 0 [ ] bootstd_drv |-- bootstd bootmeth 0 [ ] bootmeth_extlinux | |-- extlinux bootmeth 1 [ ] bootmeth_script | |-- script bootmeth 2 [ ] bootmeth_efi_mgr | |-- efi_mgr bootmeth 3 [ ] bootmeth_efi | |-- efi bootmeth 4 [ ] bootmeth_pxe | `-- pxe efi 0 [ ] EFI block driver `-- efi
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Re: WD MyCloud Gen2 (Glacier, Armada 375) February 24, 2026 01:18PM |
Admin Registered: 15 years ago Posts: 20,119 |
Could not get PHY for mdio@c0054: addr 0 mvpp2 mvpp2-0: cannot connect to phy Using mvpp2-0 deviceWe'll try another test.
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Re: WD MyCloud Gen2 (Glacier, Armada 375) February 25, 2026 04:10PM |
Admin Registered: 15 years ago Posts: 20,119 |
sha256: 634446b925d438f4d7047e5af26b718d4e9cf25206e0707146cc3e13fe986b70
uboot.2026.01-tld-1.wd-glacier.kwb uboot.2025.10-tld-1.wd-glacier.boot.cmd uboot.2025.10-tld-1.wd-glacier.boot.scr README.txt
kwboot -t -a -B 115200 /dev/ttyUSB0 -b uboot.2026.01-tld-1.wd-glacier.kwbNote: the serial device ttyUSB0 is typical for Debian-based distro. On other distro it might be different (see detailed kwboot example here).
dm tree usb start usb part sata init sata part dm treePlease post the entire serial console log here.
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ygi
Re: WD MyCloud Gen2 (Glacier, Armada 375) February 26, 2026 07:04AM |
kwboot -t -a -B 115200 /dev/ttyUSB0 -b Downloads/uboot.2026.01-tld-1.wd-glacier.bodhi.260225/uboot.2026.01-tld-1.wd-glacier.kwb
kwboot version 2026.01
Detected kwbimage v1 with SPI boot signature
Patching image boot signature to UART
Aligning image header to Xmodem block size
Sending boot message. Please reboot the target...-
Sending boot image header (92032 bytes)...
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97 % [................... ]
Done
General initialization - Version: 1.0.0
High speed PHY - Version: 0.1.1 (COM-PHY-V20)
USB2 UTMI PHY initialized succesfully
USB2 UTMI PHY initialized succesfully
High speed PHY - Ended Successfully
DDR3 Training Sequence - Ver 5.7.1
DDR3 Training Sequence - Run with PBS.
DDR3 Training Sequence - Ended Successfully
Sending boot image data (502844 bytes)...
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Done
Finishing transfer
[Type Ctrl-\ + c to quit]
U-Boot 2026.01-tld-1 (Feb 25 2026 - 13:48:32 -0800)
Western Digital MyCloud Gen2 (Glacier)
SoC: MV88F6720-A0 at 800 MHz
Model: WD MyCloud Gen2
DRAM: 512 MiB (534 MHz, 16-bit, ECC not enabled)
Core: 27 devices, 18 uclasses, devicetree: separate
MMC:
Loading Environment from nowhere... OK
Model: WD MyCloud Gen2
Net:
Warning: mvpp2-0 (eth0) using random MAC address - aa:02:df:92:59:72
eth0: mvpp2-0
Hit any key to stop autoboot: 0
WD-Glacier> dm tree
Class Seq Probed Driver Name
-----------------------------------------------------------
root 0 [ + ] root_driver root_driver
simple_bus 0 [ + ] simple_bus |-- soc
simple_bus 1 [ + ] simple_bus | `-- internal-regs
mdio 0 [ + ] mvmdio | |-- mdio@c0054
eth_phy_ge 0 [ + ] eth_phy_generic_drv | | `-- ethernet-phy@0
misc 0 [ + ] mvpp2_base | |-- ethernet@f0000
ethernet 0 [ + ] mvpp2 | | `-- mvpp2-0
bootdev 0 [ ] eth_bootdev | | `-- mvpp2-0.bootdev
spi 0 [ ] mvebu_spi | |-- spi@10600
spi_flash 0 [ ] jedec_spi_nor | | `-- spi-flash@0
i2c 0 [ ] i2c_mvtwsi | |-- i2c@11000
i2c 1 [ ] i2c_mvtwsi | |-- i2c@11100
serial 0 [ + ] ns16550_serial | |-- serial@12000
gpio 0 [ ] gpio_mvebu | |-- gpio@18100
gpio 1 [ ] gpio_mvebu | |-- gpio@18140
gpio 2 [ ] gpio_mvebu | |-- gpio@18180
syscon 0 [ ] mvebu-system-control | |-- system-controller@18200
reset 0 [ ] mvebu-reset | | `-- mvebu-reset
timer 0 [ + ] orion_timer | |-- timer@20300
usb 0 [ ] ehci_mvebu | |-- usb@54000
usb 1 [ ] xhci_mvebu | |-- usb@58000
ahci 0 [ ] sata_mv_ahci | `-- sata@a0000
bootstd 0 [ ] bootstd_drv |-- bootstd
bootmeth 0 [ ] bootmeth_extlinux | |-- extlinux
bootmeth 1 [ ] bootmeth_script | |-- script
bootmeth 2 [ ] bootmeth_efi_mgr | |-- efi_mgr
bootmeth 3 [ ] bootmeth_efi | |-- efi
bootmeth 4 [ ] bootmeth_pxe | `-- pxe
efi 0 [ ] EFI block driver `-- efi
WD-Glacier> usb start
starting USB...
USB EHCI 1.00
MVEBU XHCI INIT controller @ 0xf105b880
Starting the controller
USB XHCI 1.00
cannot reset port 1!?
Bus usb@54000: 1 USB Device(s) found
Bus usb@58000: 2 USB Device(s) found
scanning usb for storage devices... 1 Storage Device(s) found
WD-Glacier> usb part
Partition Map for usb device 0 -- Partition Type: EFI
Part Start LBA End LBA Name
Attributes
Type GUID
Partition GUID
1 0x00000800 0x747067ff "primary"
attrs: 0x0000000000000000
type: 0fc63daf-8483-4772-8e79-3d69d8477de4
guid: 321b591e-d965-4362-8a79-b535964a9fd1
WD-Glacier> sata init
Err: Failed to identify SATA device 0
WD-Glacier> sata part
Failed to wait for completion on port 0
ATA operation timed out
Failed to wait for completion on port 0
ATA operation timed out
Disk sata@a0000.blk not ready
Failed to wait for completion on port 1
ATA operation timed out
Failed to wait for completion on port 1
ATA operation timed out
Disk sata@a0000.blk not ready
no sata partition table available
WD-Glacier> dm tree
Class Seq Probed Driver Name
-----------------------------------------------------------
root 0 [ + ] root_driver root_driver
simple_bus 0 [ + ] simple_bus |-- soc
simple_bus 1 [ + ] simple_bus | `-- internal-regs
mdio 0 [ + ] mvmdio | |-- mdio@c0054
eth_phy_ge 0 [ + ] eth_phy_generic_drv | | `-- ethernet-phy@0
misc 0 [ + ] mvpp2_base | |-- ethernet@f0000
ethernet 0 [ + ] mvpp2 | | `-- mvpp2-0
bootdev 0 [ ] eth_bootdev | | `-- mvpp2-0.bootdev
spi 0 [ ] mvebu_spi | |-- spi@10600
spi_flash 0 [ ] jedec_spi_nor | | `-- spi-flash@0
i2c 0 [ ] i2c_mvtwsi | |-- i2c@11000
i2c 1 [ ] i2c_mvtwsi | |-- i2c@11100
serial 0 [ + ] ns16550_serial | |-- serial@12000
gpio 0 [ ] gpio_mvebu | |-- gpio@18100
gpio 1 [ ] gpio_mvebu | |-- gpio@18140
gpio 2 [ ] gpio_mvebu | |-- gpio@18180
syscon 0 [ ] mvebu-system-control | |-- system-controller@18200
reset 0 [ ] mvebu-reset | | `-- mvebu-reset
timer 0 [ + ] orion_timer | |-- timer@20300
usb 0 [ + ] ehci_mvebu | |-- usb@54000
usb_hub 0 [ + ] usb_hub | | `-- usb_hub
usb 1 [ + ] xhci_mvebu | |-- usb@58000
usb_hub 1 [ + ] usb_hub | | `-- usb_hub
usb_mass_s 0 [ + ] usb_mass_storage | | `-- usb_mass_storage
blk 0 [ + ] usb_storage_blk | | |-- usb_mass_storage.lun0
partition 0 [ + ] blk_partition | | | `-- usb_mass_storage.lun0:1
bootdev 1 [ ] usb_bootdev | | `-- usb_mass_storage.lun0.bootdev
ahci 0 [ + ] sata_mv_ahci | `-- sata@a0000
blk 1 [ ] sata_mv_blk | |-- sata@a0000.blk
bootdev 2 [ ] sata_bootdev | |-- sata@a0000.bootdev
blk 2 [ ] sata_mv_blk | `-- sata@a0000.blk
bootstd 0 [ ] bootstd_drv |-- bootstd
bootmeth 0 [ ] bootmeth_extlinux | |-- extlinux
bootmeth 1 [ ] bootmeth_script | |-- script
bootmeth 2 [ ] bootmeth_efi_mgr | |-- efi_mgr
bootmeth 3 [ ] bootmeth_efi | |-- efi
bootmeth 4 [ ] bootmeth_pxe | `-- pxe
efi 0 [ ] EFI block driver `-- efi
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Re: WD MyCloud Gen2 (Glacier, Armada 375) February 26, 2026 02:31PM |
Admin Registered: 15 years ago Posts: 20,119 |
ahci 0 [ + ] sata_mv_ahci | `-- sata@a0000 blk 1 [ ] sata_mv_blk | |-- sata@a0000.blk bootdev 2 [ ] sata_bootdev | |-- sata@a0000.bootdev blk 2 [ ] sata_mv_blk | `-- sata@a0000.blk
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ygi
Re: WD MyCloud Gen2 (Glacier, Armada 375) February 26, 2026 05:16PM |
Disk /dev/sda: 1.82 TiB, 2000398934016 bytes, 3907029168 sectors Disk model: WDC WD20EFRX-68E Units: sectors of 1 * 512 = 512 bytes Sector size (logical/physical): 512 bytes / 4096 bytes I/O size (minimum/optimal): 4096 bytes / 4096 bytes Disklabel type: gpt Disk identifier: 003E1597-48FB-468C-AC70-AB21C0FA6CFF Device Start End Sectors Size Type /dev/sda1 2048 1953791 1951744 953M Linux filesystem /dev/sda2 7813120 3907028991 3899215872 1.8T Linux filesystem /dev/sda3 1953792 7813119 5859328 2.8G Linux filesystem
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Re: WD MyCloud Gen2 (Glacier, Armada 375) February 27, 2026 01:40PM |
Admin Registered: 15 years ago Posts: 20,119 |
sd-gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>, <&gpio2 2 GPIO_ACTIVE_HIGH>;
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ygi
Re: WD MyCloud Gen2 (Glacier, Armada 375) February 27, 2026 03:41PM |
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Re: WD MyCloud Gen2 (Glacier, Armada 375) February 27, 2026 06:36PM |
Admin Registered: 15 years ago Posts: 20,119 |