Problems with Stora MS2000/MS2110 NAND replacement

Device 0: nand0, sector size 128 KiB

  Page size       2048 b

  OOB size          64 b

  Erase size    131072 b

  subpagesize      512 b

  options     0x4000101c

  bbt options 0x00008000





Device 0: nand0, sector size 128 KiB

  Page size       2048 b

  OOB size          64 b

  Erase size    131072 b

  subpagesize      512 b

  options     0x40001014

  bbt options 0x00008000

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Boot from NAND Flash

In this boot method, a boot image must be located on the first page of the NAND flash. The main header must exist at offset 0, and an extension header is mandatory for this boot device, to perform DDR initialization (since the image must be copied to the DDR to be executed, and it cannot be executed directly from NAND flash).
In this boot mode, <NFActCEnBoot> field in the NAND Flash Control Register
(Table 613 p. 676) is set to 1, which enables the NAND flash controller to hold the CEn signal asserted throughout the entire read phase.
The source image must be located at the offset specified by the main header.
The main header, extension header, and source image must contain valid checksum values.
The source image is downloaded to the DDR byte-by-byte, using a NAND flash software protocol.
Since there are different types of NAND flash devices, with different read command sequences, the bootROM implements a detection mechanism, to support most of the NAND flash types. The bootROM tries to read the first 512 bytes in four different ways, and uses the main header checksum check as a success indication.
Following are the four types of NAND flash read commands used, listed in the order they are tried by the bootROM:
Table 79: Types of NAND Flash Read Commands Supported
Note

NAND Flash Type
Read Command Sequence
1
Large pages
5 address cycles with 0x30 command trailer
Command 0x00, Address 0–7, Address 8–11, Address 12–19, Address 20–27, Address 28 and above, Command 0x30 NOTE: For pages larger than 2K, the size should be indicated in
the main header of the BootROM.
2
512 byte pages 3 address cycles
Plane A (Address bit-8 = 0): Command 0x00, Address 0–7, Address 9–16, Address 17–24
Plane B (Address bit-8 = 1): Command 0x01, Address 0–7, Address 9–16, Address 17–24
3
Large pages
4 address cycles with 0x30 command trailer
Command 0x00, Address 0–7, Address 8–11, Address 12–19, Address 20–27, Command 0x30
NOTE: For pages larger than 2K, the size should be indicated in
the main header of the BootROM.
4
512 byte pages 4 address cycles
Plane A (Address bit-8 = 0): Command 0x00, Address 0–7, Address 9–16, Address 17–24, Address 25–26
Plane B (Address bit-8 = 1): Command 0x01, Address 0–7, Address 9–16, Address 17–24, Address 25–26
The bootROM tries to boot from four types of NAND flash devices four times (a total of 16 times). The first eight trials are performed with ECC calculation and the last eight trials are performed skipping ECC correction. A NAND flash reset (using the command 0xFF) is performed before each boot trial.
Copyright © 2008 Marvell Doc. No. MV-S104860-U0 Rev. C December 2, 2008, Preliminary Document Classification: Proprietary Information Page 301
88F6180/88F619x/88F6281 Functional Specifications
On each trial, the bootROM checks the 32-bit checksum on the image copied to the RAM. If the checksum fails, the bootROM registers the error, increments the retry count, and restarts the boot process. The bootROM supports both 4-bit RS ECC (Reed-Solomon Error Correcting Code) and 1-bit Hamming ECC (Error Correcting Code). For Large Page NAND flash devices, RS ECC is used, while for small page devices, Hamming ECC is used.
The following are the ECC algorithms supported per NAND flash types.
Table 80: Types of ECC Protocols Supported per Flash Type
Bad Block Management
The BootROM supports bad block skipping. Before reading from a block, it is verified to be a good block, by checking the appropriate OOB byte (or bytes) in the Spare area to be 0xFF.
For the 512B page devices, the number of pages per block is fixed at 32 (and thus block size is 16 KB).
For Large page devices (2 KB and over), the block size, pages per block number, and the technology used (cell type is MLC or SLC) are read at runtime using the READID command (in bytes 3 and 4).
The following are the OOB locations checked by the bootROM based on the type of NAND flash selected through the reset strap.
Table 81: Bad Block Indicators per NAND Flash Cell Type

NAND Flash Type
Read Command Sequence
1
Large pages
4 or 5 address cycles with 0x30 command trailer
RS-ECC with 4-bit detection/correction per 512B of data.
2
512 byte page
3 and 4 address cycles
Hamming with 2-bit detection, with 1-bit correction per 256B of data (23-bit ECC).
NAND Flash Type
Read Command Sequence
1
Large page MLC devices
Byte[0] of the spare area in the last page of the block (For a good block, the byte should be equal to 0xFF).
2
Large page SLC devices
Byte[0] and Byte[5] of the spare area in the first and second pages of the block (For a good block, both bytes should be equal to 0xFF).
3
512B page SLC devices
Byte[5] of the spare area in the first and second pages of the block (For a good block, the bytes should be equal to 0xFF).

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Serial Console & JTAG console

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         __  __                      _ _
        |  \/  | __ _ _ ____   _____| | |
        | |\/| |/ _` | '__\ \ / / _ \ | |
        | |  | | (_| | |   \ V /  __/ | |
        |_|  |_|\__,_|_|    \_/ \___|_|_|
 _   _     ____              _
| | | |   | __ )  ___   ___ | |_ 
| | | |___|  _ \ / _ \ / _ \| __| 
| |_| |___| |_) | (_) | (_) | |_ 
 \___/    |____/ \___/ \___/ \__| 
 ** MARVELL BOARD: RD-88F6281A LE 

U-Boot 1.1.4 (Sep  4 2009 - 09:36:11) Marvell version: 3.4.14

U-Boot code: 00600000 -> 0067FFF0  BSS: -> 006CEE60

Soc: MV88F6281 Rev 3 (DDR2)
CPU running @ 1000Mhz L2 running @ 333Mhz
SysClock = 333Mhz , TClock = 200Mhz 

DRAM CAS Latency = 5 tRP = 5 tRAS = 18 tRCD=6
DRAM CS[0] base 0x00000000   size  64MB 
DRAM CS[1] base 0x04000000   size  64MB 
DRAM Total size 128MB  16bit width
Flash:  0 kB
Addresses 8M - 0M are saved for the U-Boot usage.
Mem malloc Initialization (8M - 7M): Done
NAND:256 MB
CRC in Flash: e13ef249, Calculated CRC: e13ef249

CPU : Marvell Feroceon (Rev 1)