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a10 sata clock patch

Posted by guillaume 
a10 sata clock patch
September 13, 2012 02:28PM
Hi,

Looks like i have found the/a sata bug ;-)

diff --git a/arch/arm/mach-sun4i/clock/clock.c b/arch/arm/mach-sun4i/clock/clock.c
index 4df915e..13842eb 100755
--- a/arch/arm/mach-sun4i/clock/clock.c
+++ b/arch/arm/mach-sun4i/clock/clock.c
@@ -178,11 +178,7 @@ int clk_init(void)
 
         /* sata pll set to 960mhz for c ver. */
         tmpSclk = &ccu_sys_clk[AW_SYS_CLK_PLL6];
-        #if(USE_PLL6M_REPLACE_PLL4)
-        tmpSclk->clk->rate  = 960000000;
-        #else
         tmpSclk->clk->rate  = 600000000;
-        #endif
         tmpSclk->set_clk(tmpSclk->clk);
         tmpSclk->clk->onoff = AW_CCU_CLK_ON;
         tmpSclk->set_clk(tmpSclk->clk);


Sata is working on my v1.7 now, sata2ΒΈ 3Gbps.
Previously it was always resetting.

It was not a problem in sw_ahci_platform but in the PLL6 clock init.
IC VersC was initialising the clock too high.

i let you try.


On my v1.7 (nothing change on v1.3, it's an IC VersB)
<6>sw_ahci sw_ahci.0: controller can't do PMP, turning off CAP_PMP
[   24.790000] sw_ahci sw_ahci.0: controller can't do PMP, turning off CAP_PMP
<4>sw_ahci sw_ahci.0: forcing PORTS_IMPL to 0x1
[   24.820000] sw_ahci sw_ahci.0: forcing PORTS_IMPL to 0x1
<6>sw_ahci sw_ahci.0: AHCI 0001.0100 32 slots 1 ports 3 Gbps 0x1 impl platform mode
[   24.840000] sw_ahci sw_ahci.0: AHCI 0001.0100 32 slots 1 ports 3 Gbps 0x1 impl platform mode
<6>sw_ahci sw_ahci.0: flags: ncq sntf pm led clo only pio slum part ccc 
[   24.860000] sw_ahci sw_ahci.0: flags: ncq sntf pm led clo only pio slum part ccc 
<6>scsi0 : sw_ahci_platform
[   24.890000] scsi0 : sw_ahci_platform
<6>ata1: SATA max UDMA/133 mmio [mem 0x01c18000-0x01c18fff] port 0x100 irq 56
[   24.910000] ata1: SATA max UDMA/133 mmio [mem 0x01c18000-0x01c18fff] port 0x100 irq 56
<6>ata1: SATA link up 3.0 Gbps (SStatus 123 SControl 300)
[   25.300000] ata1: SATA link up 3.0 Gbps (SStatus 123 SControl 300)
<6>ata1.00: ATA-7: INTEL SSDSA2M080G2GC, 2CV102M3, max UDMA/133
[   25.310000] ata1.00: ATA-7: INTEL SSDSA2M080G2GC, 2CV102M3, max UDMA/133
<6>ata1.00: 156301488 sectors, multi 1: LBA48 NCQ (depth 31/32)
[   25.320000] ata1.00: 156301488 sectors, multi 1: LBA48 NCQ (depth 31/32)
<6>ata1.00: configured for UDMA/133
[   25.340000] ata1.00: configured for UDMA/133
<5>scsi 0:0:0:0: Direct-Access     ATA      INTEL SSDSA2M080 2CV1 PQ: 0 ANSI: 5
[   25.370000] scsi 0:0:0:0: Direct-Access     ATA      INTEL SSDSA2M080 2CV1 PQ: 0 ANSI: 5
<5>sd 0:0:0:0: [sda] 156301488 512-byte logical blocks: (80.0 GB/74.5 GiB)
[   25.410000] sd 0:0:0:0: [sda] 156301488 512-byte logical blocks: (80.0 GB/74.5 GiB)
<5>sd 0:0:0:0: [sda] Write Protect is off
[   25.440000] sd 0:0:0:0: [sda] Write Protect is off
<7>sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
<5>sd 0:0:0:0: [sda] Write cache: enabled, read cache: enabled, doesn't support DPO or FUA
[   25.470000] sd 0:0:0:0: [sda] Write cache: enabled, read cache: enabled, doesn't support DPOA
<6> sda: sda1
[   25.540000]  sda: sda1
<5>sd 0:0:0:0: [sda] Attached SCSI disk
[   25.570000] sd 0:0:0:0: [sda] Attached SCSI disk
Re: a10 sata clock patch
September 14, 2012 09:49AM
Awesome work!

I look forward to implementing this patch ASAP
Re: a10 sata clock patch
September 17, 2012 04:17PM
Guillaume,

hi, thanks for your efforts ...

i've posted a link to your solution on the SATA bug thread on GIT for the A10 source code

if you want to why not have a bash at submitting the patch on GIT .. hopefully yhen once its committed then everyone will get the benefit in the source

here are a couple of links

https://github.com/amery/linux-allwinner/issues/40

https://github.com/amery/linux-allwinner

rgds

ian
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