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U-boot MT7621A MEMPLL 3PLL mode calibration fail

Posted by Alansbor 
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Alansbor
U-boot MT7621A MEMPLL 3PLL mode calibration fail
November 22, 2024 10:27AM
Hi all.

I am working with a board under TM7621A

EEPROM memory GD25Q256C
Memory DDR2 W9725G6KB-25 DDR2-800

I assemble the project as standard:
1. I take it from github u-boot
2. Run make menuconfig, save the .config file
3. make

the project runs without errors and collects many bin files including u-boot-mt7621.bin

I write it into the GD25Q256C through the programmer

I get the following through the terminal: 

===================================================================

     		MT7621   stage1 code Mar 12 2015 14:43:30 (ASIC)

     		CPU=500000000 HZ BUS=125000000 HZ

==================================================================

Change MPLL source from XTAL to CR...

do MEMPLL setting..

MEMPLL Config : 0x31000000

3PLL mode + External loopback

=== XTAL-40Mhz === DDR-800Mhz ===

PLL3 FB_DL: 0x14, 1/0 = 609/415 51000000

MEMPLL 3PLL mode calibration fail

do DDR setting..[01F40000]

Apply DDR2 Setting...(use default AC)

          0    8   16   24   32   40   48   56   64   72   80   88   96  104  112  120

      --------------------------------------------------------------------------------

0000:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0

0001:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0

0002:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0

0003:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0

0004:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0

0005:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0

0006:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    1    1

0007:|    0    0    0    0    0    0    0    1    1    1    1    1    1    1    1    1

0008:|    1    1    1    1    1    1    1    1    1    1    1    1    1    1    0    0

0009:|    1    1    1    1    1    1    0    0    0    0    0    0    0    0    0    0

000A:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0

000B:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0

000C:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0

000D:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0

000E:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0

000F:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0

0010:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0

0011:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0

0012:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0

0013:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0

0014:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0

0015:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0

0016:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0

0017:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0

0018:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0

0019:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0

001A:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0

001B:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0

001C:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0

001D:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0

001E:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0

001F:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0

DRAMC_DQSCTL1[0e0]=1A000000

DRAMC_DQSGCTL[124]=80000000

rank 0 coarse = 8

rank 0 fine = 56

B:|    0    0    0    0    1    1    1    0    0    0    0    0    0    0    0    0

opt_dle value:5

DRAMC_DDR2CTL[07c]=40001253

DRAMC_PADCTL4[0e4]=00000005

DRAMC_DQIDLY1[210]=00000000

DRAMC_DQIDLY2[214]=00000000

DRAMC_DQIDLY3[218]=00000000

DRAMC_DQIDLY4[21c]=00000000

DRAMC_R0DELDLY[018]=00000000

==================================================================

		RX	DQS perbit delay software calibration 

==================================================================

1.0-15 bit dq delay value

==================================================================

bit|     0  1  2  3  4  5  6  7  8  9

--------------------------------------

0 |    0 0 0 0 0 0 0 0 0 0 

10 |    0 0 0 0 0 0 

--------------------------------------

==================================================================

2.dqs window

x=pass dqs delay value (min~max)center 

y=0-7bit DQ of every group

input delay:DQS0 =0 DQS1 = 0

==================================================================

bit	DQS0	 bit      DQS1

0  (-1~-1)0  8  (-1~-1)0

1  (-1~-1)0  9  (-1~-1)0

2  (-1~-1)0  10  (-1~-1)0

3  (-1~-1)0  11  (-1~-1)0

4  (-1~-1)0  12  (-1~-1)0

5  (-1~-1)0  13  (-1~-1)0

6  (-1~-1)0  14  (-1~-1)0

7  (-1~-1)0  15  (-1~-1)0

==================================================================

3.dq delay value last

==================================================================

bit|    0  1  2  3  4  5  6  7  8   9

--------------------------------------

0 |    0 0 0 0 0 0 0 0 0 0 

10 |    0 0 0 0 0 0 

==================================================================

==================================================================

     TX  perbyte calibration 

==================================================================

DQS loop = 15, cmp_err_1 = ffffffff 

DQS loop = 14, cmp_err_1 = ffffffff 

DQS loop = 13, cmp_err_1 = ffffffff 

DQS loop = 12, cmp_err_1 = ffffffff 

DQS loop = 11, cmp_err_1 = ffffffff 

DQS loop = 10, cmp_err_1 = ffffffff 

DQS loop = 9, cmp_err_1 = ffffffff 

DQS loop = 8, cmp_err_1 = ffffffff 

DQS loop = 7, cmp_err_1 = ffffffff 

DQS loop = 6, cmp_err_1 = ffffffff 

DQS loop = 5, cmp_err_1 = ffffffff 

DQS loop = 4, cmp_err_1 = ffffffff 

DQS loop = 3, cmp_err_1 = ffffffff 

DQS loop = 2, cmp_err_1 = ffffffff 

DQS loop = 1, cmp_err_1 = ffffffff 

DQS loop = 0, cmp_err_1 = ffffffff 

DQ loop=15, cmp_err_1 = ffffffff

DQ loop=14, cmp_err_1 = ffffffff

DQ loop=13, cmp_err_1 = ffffffff

DQ loop=12, cmp_err_1 = ffffffff

DQ loop=11, cmp_err_1 = ffffffff

DQ loop=10, cmp_err_1 = ffffffff

DQ loop=9, cmp_err_1 = ffffffff

DQ loop=8, cmp_err_1 = ffffffff

DQ loop=7, cmp_err_1 = ffffffff

DQ loop=6, cmp_err_1 = ffffffff

DQ loop=5, cmp_err_1 = ffffffff

DQ loop=4, cmp_err_1 = ffffffff

DQ loop=3, cmp_err_1 = ffffffff

DQ loop=2, cmp_err_1 = ffffffff

DQ loop=1, cmp_err_1 = ffffffff

DQ loop=0, cmp_err_1 = ffffffff

byte:0, (DQS,DQ)=(8,8)

byte:1, (DQS,DQ)=(8,8)

DRAMC_DQODLY1[200]=88888888

DRAMC_DQODLY2[204]=88888888

20,data:88

[EMI] DRAMC calibration passed


===================================================================

     		MT7621   stage1 code done 

     		CPU=500000000 HZ BUS=125000000 HZ

===================================================================

PLL3 FB_DL: 0x14, 1/0 = 609/415 51000000

MEMPLL 3PLL mode calibration fail

How to beat this? What am I doing wrong?

=======
bodhi edit: correct model name in thread subject: MT7621A



Edited 1 time(s). Last edit at 11/27/2024 02:07PM by bodhi.
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bodhi
Re: U-boot TM7621A MEMPLL 3PLL mode calibration fail
November 22, 2024 03:45PM
Alansbor,

It does not sound like you're doing anything wrong. This board is actively maintained in U-Boot, so you should send this report to:

U-Boot Mailing List <u-boot@lists.denx.de>

-bodhi
===========================
Forum Wiki
bodhi's corner (buy bodhi a beer)
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Alansbor
Re: U-boot TM7621A MEMPLL 3PLL mode calibration fail
November 22, 2024 03:57PM
Hello bodhi

Thanks a lot for your help bodhi!

Report sent to the address you specified.

If you're in Sri Lanka in January - December, we'll definitely drink beer :)

Alan
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bodhi
Re: U-boot TM7621A MEMPLL 3PLL mode calibration fail
November 22, 2024 05:56PM
Alan,

You mispelled MT7621A? MediaTek is mt7621, not tm7621. I think.

-bodhi
===========================
Forum Wiki
bodhi's corner (buy bodhi a beer)
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Alansbor
Re: U-boot TM7621A MEMPLL 3PLL mode calibration fail
November 22, 2024 06:00PM
Bodhi,

you're right, the full name of the chip
MT7621AT
2138-AMAH
CTPCY159
DTPCW111

sorry.
Reply Quote
bodhi
Re: U-boot MT7621A MEMPLL 3PLL mode calibration fail
November 27, 2024 02:13PM
Alan,

If you don't get reponse from the u-boot ML, try sending again to both the ML and the maintainer (reply to your email and add the maintainer email address to TO: list). Find the email address here.

board/mediatek/mt7621/MAINTAINERS

You don't need to mention this forum.

-bodhi
===========================
Forum Wiki
bodhi's corner (buy bodhi a beer)



Edited 1 time(s). Last edit at 11/27/2024 02:19PM by bodhi.
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